1. Field of the Invention
This invention is related to the field of integrated circuit design tool software and, more particularly, to design tools for layout processing.
2. Description of the Related Art
The clock frequencies at which integrated circuits are designed to operate continue to increase over time. As a result, wire delay (the delay in propagating signals between the circuits in the integrated circuit) is increasingly an important factor in whether or not the clock frequency goals of the integrated circuit can be met.
In a typical design flow, the integrated circuit design is reduced to one or more netlists. Typically, the integrated circuit is divided, at a high level, into various blocks of functionality, each of which may be reduced to one or more netlists that, when realized as circuits, provide the functionality. Each netlist includes: (i) a list of predesigned circuits (often referred to as cells) which perform identified functions; and (ii) an identification of the interconnection between the cells, typically by using the same signal name on the output of one cell and the inputs of one or more other cells to which that output is connected. The predesigned circuits may include standard cells which perform standard logic/data flow functions (e.g. AND, OR, NAND, more complex logic functions, registers, multiplexors, etc.) which may be used throughout the integrated circuit design and/or custom circuits designed specifically for use in the circuit represented by the netlist.
The netlists are then processed with a layout tool to produce a physical layout of the integrated circuit. Each cell is placed on the layout, and nets are introduced into the layout to connect the inputs and outputs of the cells as specified in the netlist. In many cases, the layout tool may automatically generate the routing of the nets in the layout.
Due to a variety of factors (including limited wiring space, limitations in the algorithms used to automatically generate the routing, etc.), one or more nets may be routed in a less than optimum fashion. The added length of wire corresponding to the net may contribute to the delay in the circuit path which includes the net, and may cause the path to exceed the available time for evaluation. Detecting the sub-optimum routing is typically performed by engineers responsible for the integrated circuit design, by visually inspecting graphical representations of the layout and attempting to locate nets which can have their routing shortened.